CV

Lukas Rüttgers

lruettgers[at]ethz[dot]ch
Zurich, , CH

Summary

Life is not a fixed point problem. Embrace turbulence.

Education

  • Computer Science M.Sc.
    2026
    ETH Zurich
    GPA: 5.51
    Courses: Focus: ML, Math, High-performance computing, Semester project on learning lookup-table networks | PyTorch, CUDA (ongoing, subject to NDA), Machine Learning projects: Geometric Mutual Information Estimation, Spectral Clustering (see GitHub: https://github.com/MariSchn/Advanced-Machine-Learning-Projects)
  • Visiting student
    2024
    Institute for Interdisciplinary Information Sciences, Tsinghua University
    Courses: Robotics lectures (see GitHub: https://github.com/lukas-ruettgers/competence_progress_motivation) | PyTorch, TensorFlow, ROS, Isaac Gym, C++, Research in domain generalization (ML theory) (see GitHub: https://github.com/lukas-ruettgers/bachelor-thesis)
  • Computer Science B.Sc.
    2024
    RWTH Aachen University
    GPA: 1.0 (top 2% of the year)
    Courses: Minor in Mechanical Engineering and Math: Mechanics, Machine Design, Numerical Math, Focus Area in Machine Learning and Robotics, Hardware Project: RFID Scanner on Atmel AVR Microcontroller

Work Experience

  • Working student
    2025 - present
    QuantCo Schweiz GmbH
  • Research assistant
    2023 - 2023
    Chair of Machine Learning, RWTH Aachen University
    • Action Model Learning in RL | Linux, Slurm, Bash
  • Working student, Desktop software engineering
    2022 - 2023
    Daten- und Systemtechnik GmbH
    • Desktop software development | Python 3.10, CI/CD
  • Working student, Network management
    2021 - 2022
    Robert Bosch GmbH
    • Maintenance administration software | JavaScript, Atlassian Bitbucket, Jira
  • Corporate student, Network configuration
    2020 - 2021
    Robert Bosch GmbH

Skills

Languages

  • German (mother tongue)
  • English (TOEFL C1)
  • Chinese (HSK4)
  • French (B2 CEFR)

Programming

  • Python 3.10 (>3 years)
  • C++17
  • CUDA

Publications

  • Light Differentiable Logic Gate Networks
    2025
    Under review
    We reparametrize differentiable logic gate networks to make them more scalable in depth and complexity.